Static Timing Analysis
Predict timing without vectors and catch violations early.
What STA Does
STA evaluates all timing paths in a design using library models and constraints. It reports setup, hold, and recovery/removal checks without requiring simulation vectors.
Key outputs include worst negative slack (WNS), total negative slack (TNS), and path-based diagnostics.
Core Concepts
Setup checks ensure data arrives before the clock edge.
Hold checks ensure data remains stable after the clock edge.
Clock uncertainty, OCV derates, and RC parasitics add realism to signoff.
Practical Checklist
Fix setup with faster cells, buffering, or path restructuring.
Fix hold with delay insertion or clock path tuning.
Validate constraints and clock definitions before deep optimization.